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1 | (38) |
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1 | (2) |
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The Main Components of a Computer |
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3 | (1) |
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An Example System: Wading Through the Jargon |
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4 | (9) |
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13 | (1) |
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14 | (14) |
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Generation Zero: Mechanical Calculating Machines (1642-1945) |
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15 | (2) |
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The First Generation: Vacuum Tube Computers (1945-1953) |
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17 | (4) |
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The Second Generation: Transistorized Computers (1954-1965) |
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21 | (3) |
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The Third Generation: Integrated Circuit Computers (1965-1980) |
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24 | (1) |
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The Fourth Generation: VLSI Computers (1980-????) |
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24 | (3) |
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27 | (1) |
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The Computer Level Hierarchy |
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28 | (2) |
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30 | (2) |
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32 | (7) |
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34 | (1) |
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34 | (1) |
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35 | (1) |
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Review of Essential Terms and Concepts |
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36 | (1) |
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37 | (2) |
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Data Representation in Computer Systems |
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39 | (70) |
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39 | (1) |
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Positional Numbering Systems |
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40 | (1) |
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Decimal to Binary Conversions |
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40 | (6) |
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Converting Unsigned Whole Numbers |
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41 | (2) |
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43 | (3) |
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Converting between Power-of-Two Radices |
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46 | (1) |
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Signed Integer Representation |
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46 | (17) |
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46 | (6) |
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52 | (6) |
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Unsigned Versus Signed Numbers |
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58 | (1) |
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Computers, Arithmetic, and Booth's Algorithm |
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58 | (4) |
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62 | (1) |
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Floating-Point Representation |
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63 | (11) |
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64 | (2) |
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Floating-Point Arithmetic |
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66 | (1) |
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67 | (1) |
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The IEEE-754 Floating-Point Standard |
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68 | (3) |
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Range, Precision, and Accuracy |
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71 | (1) |
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Additional Problems with Floating-Point Numbers |
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71 | (3) |
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74 | (7) |
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74 | (2) |
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76 | (2) |
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78 | (2) |
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80 | (1) |
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Error Detection and Correction |
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81 | (28) |
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81 | (3) |
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84 | (6) |
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90 | (1) |
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91 | (1) |
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91 | (1) |
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92 | (1) |
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Review of Essential Terms and Concepts |
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93 | (1) |
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94 | (15) |
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Boolean Algebra and Digital Logic |
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109 | (68) |
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109 | (1) |
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110 | (8) |
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111 | (1) |
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112 | (2) |
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Simplification of Boolean Expressions |
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114 | (1) |
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115 | (1) |
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Representing Boolean Functions |
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116 | (2) |
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118 | (3) |
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118 | (1) |
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119 | (1) |
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120 | (1) |
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121 | (2) |
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Digital Circuits and Their Relationship to Boolean Algebra |
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121 | (1) |
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122 | (1) |
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123 | (8) |
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123 | (1) |
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Examples of Typical Combinational Circuits |
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124 | (7) |
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131 | (20) |
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131 | (1) |
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131 | (1) |
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132 | (3) |
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135 | (5) |
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Examples of Sequential Circuits |
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140 | (5) |
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An Application of Sequential Logic: Convolutional Coding and Viterbi Detection |
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145 | (6) |
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151 | (26) |
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152 | (1) |
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152 | (2) |
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154 | (1) |
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Review of Essential Terms and Concepts |
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154 | (1) |
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155 | (22) |
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MARIE: An Introduction to a Simple Computer |
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177 | (66) |
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177 | (1) |
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CPU Basics and Organization |
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177 | (2) |
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178 | (1) |
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179 | (1) |
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179 | (1) |
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179 | (4) |
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183 | (2) |
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The Input/Output Subsystem |
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185 | (1) |
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Memory Organization and Addressing |
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186 | (3) |
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189 | (1) |
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190 | (8) |
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190 | (1) |
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190 | (3) |
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Instruction Set Architecture |
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193 | (2) |
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Register Transfer Notation |
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195 | (3) |
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198 | (5) |
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The Fetch-Decode-Execute Cycle |
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198 | (1) |
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Interrupts and the Instruction Cycle |
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199 | (4) |
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203 | (1) |
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203 | (3) |
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A Discussion on Assemblers |
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206 | (3) |
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206 | (2) |
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Why Use Assembly Language? |
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208 | (1) |
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Extending our Instruction Set |
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209 | (5) |
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A Discussion on Decoding: Hardwired Versus Microprogrammed Control |
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214 | (9) |
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214 | (2) |
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216 | (1) |
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217 | (6) |
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Real-World Examples of Computer Architectures |
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223 | (20) |
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224 | (6) |
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230 | (3) |
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233 | (1) |
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234 | (1) |
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235 | (1) |
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Review of Essential Terms and Concepts |
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236 | (1) |
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237 | (6) |
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A Closer Look at Instruction Set Architectures |
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243 | (38) |
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243 | (1) |
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243 | (11) |
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Design Decisions for Instruction Sets |
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244 | (1) |
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245 | (2) |
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Internal Storage in the CPU: Stacks Versus Registers |
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247 | (1) |
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Number of Operands and Instruction Length |
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248 | (4) |
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252 | (2) |
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254 | (3) |
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254 | (1) |
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254 | (1) |
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Boolean Logic Instructions |
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255 | (1) |
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Bit Manipulation Instructions |
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255 | (1) |
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Input/Output Instructions |
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256 | (1) |
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Instructions for Transfer of Control |
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256 | (1) |
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Special Purpose Instructions |
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256 | (1) |
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Instruction Set Orthogonality |
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256 | (1) |
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257 | (4) |
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257 | (1) |
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258 | (3) |
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Instruction-Level Pipelining |
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261 | (5) |
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Real-World Examples of ISAs |
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266 | (15) |
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266 | (1) |
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267 | (1) |
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267 | (4) |
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271 | (1) |
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272 | (1) |
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273 | (1) |
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Review of Essential Terms and Concepts |
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274 | (1) |
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275 | (6) |
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281 | (46) |
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281 | (1) |
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281 | (2) |
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283 | (2) |
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285 | (1) |
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285 | (17) |
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287 | (8) |
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295 | (1) |
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Effective Access Time and Hit Ratio |
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296 | (1) |
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When Does Caching Break Down? |
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297 | (1) |
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297 | (3) |
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Instruction and Data Caches |
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300 | (1) |
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301 | (1) |
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302 | (14) |
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303 | (7) |
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Effective Access Time Using Paging |
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310 | (1) |
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Putting It All Together: Using Cache, TLBs, and Paging |
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311 | (2) |
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Advantages and Disadvantages of Paging and Virtual Memory |
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313 | (1) |
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314 | (1) |
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Paging Combined with Segmentation |
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315 | (1) |
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A Real-World Example of Memory Management |
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316 | (11) |
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317 | (1) |
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318 | (1) |
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318 | (1) |
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Review of Essential Terms and Concepts |
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319 | (1) |
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320 | (7) |
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Input/Output and Storage Systems |
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327 | (80) |
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327 | (1) |
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328 | (1) |
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328 | (1) |
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329 | (12) |
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331 | (7) |
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Character I/O Versus Block I/O |
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338 | (1) |
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338 | (3) |
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341 | (4) |
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Parallel Data Transmission |
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341 | (4) |
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345 | (1) |
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345 | (8) |
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347 | (4) |
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351 | (2) |
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353 | (6) |
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353 | (4) |
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357 | (1) |
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358 | (1) |
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Optical Disk Recording Methods |
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358 | (1) |
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359 | (5) |
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364 | (8) |
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365 | (1) |
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366 | (1) |
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366 | (1) |
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367 | (1) |
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368 | (1) |
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369 | (1) |
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370 | (1) |
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371 | (1) |
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372 | (1) |
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The Future of Data Storage |
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372 | (35) |
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377 | (1) |
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377 | (1) |
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378 | (1) |
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Review of Essential Terms and Concepts |
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379 | (2) |
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381 | (26) |
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407 | (54) |
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407 | (1) |
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408 | (12) |
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Operating Systems History |
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409 | (5) |
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414 | (2) |
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Operating System Services |
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416 | (4) |
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420 | (8) |
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421 | (3) |
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Subsystems and Partitions |
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424 | (2) |
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Protected Environments and the Evolution of Systems Architectures |
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426 | (2) |
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428 | (11) |
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428 | (3) |
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431 | (1) |
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432 | (2) |
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434 | (4) |
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438 | (1) |
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439 | (6) |
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445 | (6) |
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451 | (10) |
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453 | (2) |
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455 | (1) |
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456 | (1) |
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Review of Essential Terms and Concepts |
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456 | (1) |
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457 | (4) |
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Alternative Architectures |
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461 | (44) |
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461 | (1) |
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462 | (5) |
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467 | (4) |
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Parallel and Multiprocessor Architectures |
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471 | (16) |
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472 | (2) |
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474 | (1) |
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475 | (5) |
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Shared Memory Multiprocessors |
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480 | (4) |
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484 | (3) |
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Alternative Parallel Processing Approaches |
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487 | (7) |
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487 | (2) |
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489 | (3) |
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492 | (2) |
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494 | (11) |
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496 | (1) |
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497 | (1) |
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497 | (2) |
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Review of Essential Terms and Concepts |
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499 | (1) |
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500 | (5) |
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Topics in Embedded Systems |
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505 | (36) |
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505 | (2) |
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An Overview of Embedded Hardware |
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507 | (19) |
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Off-the-Shelf Embedded System Hardware |
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507 | (4) |
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511 | (7) |
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Custom-Designed Embedded Hardware |
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518 | (8) |
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An Overview of Embedded Software |
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526 | (15) |
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Embedded Systems Memory Organization |
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527 | (1) |
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Embedded Operating Systems |
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528 | (3) |
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Embedded Systems Software Development |
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531 | (2) |
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533 | (2) |
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535 | (1) |
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536 | (1) |
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Review of Essential Terms and Concepts |
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537 | (1) |
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538 | (3) |
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Performance Measurement and Analysis |
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541 | (50) |
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541 | (1) |
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Computer Performance Equations |
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542 | (1) |
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Mathematical Preliminaries |
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543 | (8) |
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544 | (5) |
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The Statistics and Semantics |
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549 | (2) |
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551 | (16) |
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Clock Rate, MIPS, and FLOPS |
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552 | (2) |
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Synthetic Benchmarks: Whetstone, Linpack, and Dhrystone |
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554 | (1) |
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Standard Performance Evaluation Corporation Benchmarks |
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555 | (4) |
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Transaction Processing Performance Council Benchmarks |
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559 | (7) |
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566 | (1) |
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CPU Performance Optimization |
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567 | (7) |
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567 | (3) |
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Use of Good Algorithms and Simple Code |
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570 | (4) |
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574 | (17) |
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Understanding the Problem |
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574 | (1) |
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575 | (1) |
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576 | (6) |
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582 | (1) |
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583 | (1) |
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584 | (1) |
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Review of Essential Terms and Concepts |
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585 | (1) |
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585 | (6) |
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Network Organization and Architecture |
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591 | (78) |
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591 | (1) |
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Early Business Computer Networks |
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591 | (1) |
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Early Academic and Scientific Networks: The Roots and Architecture of the Internet |
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592 | (4) |
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Network Protocols I: ISO/OSI Protocol Unification |
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596 | (6) |
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597 | (1) |
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598 | (4) |
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Network Protocols II: TCP/IP Network Architecture |
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602 | (20) |
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The IP Layer for Version 4 |
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602 | (4) |
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The Trouble with IP Version 4 |
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606 | (4) |
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Transmission Control Protocol |
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610 | (1) |
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611 | (4) |
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615 | (7) |
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622 | (21) |
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Physical Transmission Media |
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622 | (8) |
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630 | (1) |
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631 | (1) |
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631 | (1) |
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632 | (1) |
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633 | (1) |
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634 | (9) |
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High-Capacity Digital Links |
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643 | (9) |
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643 | (5) |
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648 | (3) |
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Asynchronous Transfer Mode |
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651 | (1) |
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652 | (17) |
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Ramping on to the Internet |
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653 | (7) |
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660 | (1) |
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661 | (1) |
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661 | (2) |
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663 | (1) |
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Review of Essential Terms and Concepts |
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663 | (2) |
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665 | (4) |
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Selected Storage Systems and Interfaces |
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669 | (26) |
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669 | (1) |
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670 | (12) |
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``Classic'' Parallel SCSI |
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671 | (4) |
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The SCSI Architecture Model-3 |
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675 | (7) |
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682 | (3) |
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685 | (1) |
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685 | (10) |
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Parallel Buses: XT to ATA |
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686 | (1) |
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Serial ATA and Serial Attached SCSI |
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687 | (1) |
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Peripheral Component Interconnect |
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688 | (1) |
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689 | (1) |
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High Performance Peripheral Interface: HiPPI |
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689 | (1) |
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690 | (1) |
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691 | (1) |
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691 | (1) |
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Review of Essential Terms and Concepts |
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692 | (1) |
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692 | (3) |
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APPENDIX A Data Structures and the Computer |
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695 | (20) |
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695 | (1) |
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A.2 Fundamental Structures |
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695 | (6) |
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695 | (2) |
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A.2.2 Queues and Linked Lists |
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697 | (1) |
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698 | (3) |
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701 | (6) |
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707 | (8) |
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710 | (1) |
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710 | (1) |
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710 | (1) |
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|
710 | (5) |
Glossary |
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715 | (42) |
Answers and Hints for Selected Exercises |
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757 | (16) |
Index |
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773 | |