Preface |
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vii | |
Part I: Fractional-N Synthesis |
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1 | (26) |
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Practical Design Aspects in Franctional-N Frequency Synthesis Design and Simulation of Franctional-N Frequency Synthesizers |
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27 | (24) |
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Monolithic CMOS Fractional-N Frequency Synthesizer Design for High Spectral Purity |
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51 | (26) |
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A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser with 35Hz Frequency Step and Quantization Noise Compensation |
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I. Bietti, G. Albasini, E. Temporite, R. Castello |
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77 | (20) |
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Implementation Aspects of Fractional-N Techniques in Cellular Handsets |
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97 | (14) |
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Fractional-N Phase Locked Loops and it's Application in the GSM System |
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G. Märzinger, B. Neurauter |
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111 | (18) |
Part II: Design for Robustness |
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129 | (2) |
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ESD for Analogue Circuit Design |
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131 | (38) |
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ESD in Smart Power Processes |
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G. Croce, A. Andreini, L. Cerati, G. Meneghesso, L. Sponion |
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169 | (38) |
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RF-ESD Co-Design for High Performance CMOS LNAs |
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207 | (20) |
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Improvement of System Robustness through EMC Optimazation |
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227 | (16) |
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Robustness in Analog Design |
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243 | (12) |
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Minimizing Undesired Coupling and Interaction in Mixed Signal ICs |
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255 | (20) |
Part III: Line and Bus Drivers J. Huijsing |
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Looking to/for Low Power ADSL Drivers in the DSLAM |
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275 | (16) |
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Class-AB Low-Distortion Drivers for ADSL |
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291 | (18) |
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Class D Self-Oscillating Line Drivers |
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309 | (24) |
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Class GIH Line Drivers for xDSL |
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333 | (26) |
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The USB 2.0 Physical Layer: Standard and Implementation |
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359 | (20) |
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K. Tam, W. Ellersick, R. Soenneker |
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379 | |