Cmos Digital Integrated Circuits

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Format: Hardcover
Pub. Date: 1995-08-01
Publisher(s): McGraw-Hill College
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Summary

"CMOS Digital Integrated Circuits: Analysis and Design" is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware.

Table of Contents

Preface vii
Introduction
1(12)
Fabrication of Mosfets
13(22)
Introduction
13(2)
Fabrication Process Flow-Basic Steps
15(7)
The CMOS n-Well Process
22(7)
Layout Design Rules
29(6)
References
33(1)
Exercise Problems
33(2)
Mos Transistor
35(76)
The Metal Oxide Semiconductor (MOS) Structure
36(4)
The MOS System under External Bias
40(4)
Structure and Operation of MOS Transistor (MOSFET)
44(12)
MOSFET Current-Voltage Characteristics
56(17)
MOSFET Scaling and Small-Geometry Effects
73(18)
MOSFET Capacitances
91(20)
References
105(1)
Exercise Problems
105(6)
Modeling of Mos Transistors Using Spice
111(23)
Basic Concepts
112(1)
The LEVEL 1 Model Equations
113(4)
The LEVEL 2 Model Equations
117(8)
The LEVEL 3 Model Equations
125(1)
Capacitance Models
126(4)
Comparison of the SPICE MOSFET Models
130(4)
References
132(1)
Exercise Problems
133(1)
Mos Inverters: Static Characteristics
134(63)
Introduction
134(9)
Resistive-Load Inverter
143(11)
Inverter with Enhancement-Type MOSFET Load
154(8)
Inverter with Depletion-Type MOSFET Load
162(13)
CMOS Inverter
175(22)
References
193(1)
Exercise Problems
194(3)
Mos Inverters: Dynamic Characteristics
197(37)
Introduction
198(1)
Delay-Time Definitions
199(3)
Calculation of Delay Times
202(12)
CMOS Ring Oscillator Circuit
214(2)
Estimation of Interconnect Parasitics
216(5)
Dynamic Power Dissipation of CMOS Inverters
221(13)
References
228(2)
Exercise Problems
230(4)
Combinational Mos Logic Circuits
234(49)
Introduction
234(1)
MOS Logic Circuits with Depletion nMOS Loads
235(15)
CMOS Logic Circuits
250(8)
Complex Logic Circuits
258(10)
CMOS Transmission Gates (TGs) and TG Logic
268(15)
References
275(2)
Exercise Problems
277(6)
Sequential Mos Logic Circuits
283(39)
Introduction
283(2)
Behavior of Bistable Elements
285(6)
The SR Latch Circuit
291(7)
Clocked Latch and Flip-Flop Circuits
298(9)
CMOS D-Latch and Edge-Triggered Flip-Flop
307(15)
References
317(1)
Exercise Problems
317(5)
Dynamic Logic Circuits
322(57)
Introduction
322(4)
Basic Principles of Pass Transistor Circuits
326(14)
Voltage Bootstrapping
340(5)
Synchronous Dynamic Circuit Techniques
345(10)
High-Performance Dynamic CMOS Circuits
355(24)
References
372(1)
Exercise Problems
373(6)
Semiconductor Memories
379(53)
Introduction
379(3)
Read-Only Memory (ROM) Circuits
382(14)
Static Read-Write Memory (SRAM) Circuits
396(19)
Dynamic Read-Write Memory (DRAM) Circuits
415(17)
References
427(1)
Exercise Problems
428(4)
BiCMOS Logic Circuits
432(47)
Introduction
432(4)
Bipolar Junction Transistor (BJT): Structure and Operation
436(16)
Dynamic Behavior of BJTs
452(8)
Basic BiCMOS Circuits: Static Behavior
460(3)
Switching Delay in BiCMOS Logic Circuits
463(6)
BiCMOS Applications
469(10)
References
474(1)
Exercise Problems
475(4)
Chip Input and Output (I/O) Circuits
479(33)
Introduction
479(1)
ESD Protection
480(3)
Input Circuits
483(6)
Output Circuits and L(di/dt) Noise
489(6)
On-Chip Clock Generation and Distribution
495(2)
Super Buffer Design
497(3)
Latch-Up and Its Prevention
500(12)
References
509(1)
Exercise Problems
509(3)
VLSI Design Methodologies
512(22)
Design Complexity vs. Design Cycle Time
512(2)
Design Flow
514(1)
Design Styles
515(9)
Design Quality
524(3)
Packaging Technology
527(1)
Computer-Aided Design Technology
528(6)
References
530(1)
Exercise Problems
531(3)
Design for Manufacturability
534(45)
Introduction
534(1)
Process Variations
535(2)
Basic Concepts and Definitions
537(8)
Design of Experiments and Performance Modeling
545(9)
Parametric Yield Estimation
554(5)
Parametric Yield Maximization
559(2)
Worst-Case Analysis
561(7)
Performance Variability Minimization
568(11)
References
573(1)
Exercise Problems
574(5)
Design for Testability
579(18)
Introduction
579(1)
Fault Types and Models
579(5)
Controllability and Observability
584(1)
Ad Hoc Testable Design Techniques
585(3)
Scan-Based Techniques
588(2)
Built-In Self Test (BIST) Techniques
590(4)
Current Monitoring IDDQ Test
594(3)
References
595(1)
Exercise Problems
595(2)
Appendix Design and Implementation of a 16-Bit Adder 597(14)
Index 611

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