Preface |
|
vii | |
|
|
1 | (12) |
|
|
13 | (22) |
|
|
13 | (2) |
|
Fabrication Process Flow-Basic Steps |
|
|
15 | (7) |
|
|
22 | (7) |
|
|
29 | (6) |
|
|
33 | (1) |
|
|
33 | (2) |
|
|
35 | (76) |
|
The Metal Oxide Semiconductor (MOS) Structure |
|
|
36 | (4) |
|
The MOS System under External Bias |
|
|
40 | (4) |
|
Structure and Operation of MOS Transistor (MOSFET) |
|
|
44 | (12) |
|
MOSFET Current-Voltage Characteristics |
|
|
56 | (17) |
|
MOSFET Scaling and Small-Geometry Effects |
|
|
73 | (18) |
|
|
91 | (20) |
|
|
105 | (1) |
|
|
105 | (6) |
|
Modeling of Mos Transistors Using Spice |
|
|
111 | (23) |
|
|
112 | (1) |
|
The LEVEL 1 Model Equations |
|
|
113 | (4) |
|
The LEVEL 2 Model Equations |
|
|
117 | (8) |
|
The LEVEL 3 Model Equations |
|
|
125 | (1) |
|
|
126 | (4) |
|
Comparison of the SPICE MOSFET Models |
|
|
130 | (4) |
|
|
132 | (1) |
|
|
133 | (1) |
|
Mos Inverters: Static Characteristics |
|
|
134 | (63) |
|
|
134 | (9) |
|
|
143 | (11) |
|
Inverter with Enhancement-Type MOSFET Load |
|
|
154 | (8) |
|
Inverter with Depletion-Type MOSFET Load |
|
|
162 | (13) |
|
|
175 | (22) |
|
|
193 | (1) |
|
|
194 | (3) |
|
Mos Inverters: Dynamic Characteristics |
|
|
197 | (37) |
|
|
198 | (1) |
|
|
199 | (3) |
|
Calculation of Delay Times |
|
|
202 | (12) |
|
CMOS Ring Oscillator Circuit |
|
|
214 | (2) |
|
Estimation of Interconnect Parasitics |
|
|
216 | (5) |
|
Dynamic Power Dissipation of CMOS Inverters |
|
|
221 | (13) |
|
|
228 | (2) |
|
|
230 | (4) |
|
Combinational Mos Logic Circuits |
|
|
234 | (49) |
|
|
234 | (1) |
|
MOS Logic Circuits with Depletion nMOS Loads |
|
|
235 | (15) |
|
|
250 | (8) |
|
|
258 | (10) |
|
CMOS Transmission Gates (TGs) and TG Logic |
|
|
268 | (15) |
|
|
275 | (2) |
|
|
277 | (6) |
|
Sequential Mos Logic Circuits |
|
|
283 | (39) |
|
|
283 | (2) |
|
Behavior of Bistable Elements |
|
|
285 | (6) |
|
|
291 | (7) |
|
Clocked Latch and Flip-Flop Circuits |
|
|
298 | (9) |
|
CMOS D-Latch and Edge-Triggered Flip-Flop |
|
|
307 | (15) |
|
|
317 | (1) |
|
|
317 | (5) |
|
|
322 | (57) |
|
|
322 | (4) |
|
Basic Principles of Pass Transistor Circuits |
|
|
326 | (14) |
|
|
340 | (5) |
|
Synchronous Dynamic Circuit Techniques |
|
|
345 | (10) |
|
High-Performance Dynamic CMOS Circuits |
|
|
355 | (24) |
|
|
372 | (1) |
|
|
373 | (6) |
|
|
379 | (53) |
|
|
379 | (3) |
|
Read-Only Memory (ROM) Circuits |
|
|
382 | (14) |
|
Static Read-Write Memory (SRAM) Circuits |
|
|
396 | (19) |
|
Dynamic Read-Write Memory (DRAM) Circuits |
|
|
415 | (17) |
|
|
427 | (1) |
|
|
428 | (4) |
|
|
432 | (47) |
|
|
432 | (4) |
|
Bipolar Junction Transistor (BJT): Structure and Operation |
|
|
436 | (16) |
|
|
452 | (8) |
|
Basic BiCMOS Circuits: Static Behavior |
|
|
460 | (3) |
|
Switching Delay in BiCMOS Logic Circuits |
|
|
463 | (6) |
|
|
469 | (10) |
|
|
474 | (1) |
|
|
475 | (4) |
|
Chip Input and Output (I/O) Circuits |
|
|
479 | (33) |
|
|
479 | (1) |
|
|
480 | (3) |
|
|
483 | (6) |
|
Output Circuits and L(di/dt) Noise |
|
|
489 | (6) |
|
On-Chip Clock Generation and Distribution |
|
|
495 | (2) |
|
|
497 | (3) |
|
Latch-Up and Its Prevention |
|
|
500 | (12) |
|
|
509 | (1) |
|
|
509 | (3) |
|
VLSI Design Methodologies |
|
|
512 | (22) |
|
Design Complexity vs. Design Cycle Time |
|
|
512 | (2) |
|
|
514 | (1) |
|
|
515 | (9) |
|
|
524 | (3) |
|
|
527 | (1) |
|
Computer-Aided Design Technology |
|
|
528 | (6) |
|
|
530 | (1) |
|
|
531 | (3) |
|
Design for Manufacturability |
|
|
534 | (45) |
|
|
534 | (1) |
|
|
535 | (2) |
|
Basic Concepts and Definitions |
|
|
537 | (8) |
|
Design of Experiments and Performance Modeling |
|
|
545 | (9) |
|
Parametric Yield Estimation |
|
|
554 | (5) |
|
Parametric Yield Maximization |
|
|
559 | (2) |
|
|
561 | (7) |
|
Performance Variability Minimization |
|
|
568 | (11) |
|
|
573 | (1) |
|
|
574 | (5) |
|
|
579 | (18) |
|
|
579 | (1) |
|
|
579 | (5) |
|
Controllability and Observability |
|
|
584 | (1) |
|
Ad Hoc Testable Design Techniques |
|
|
585 | (3) |
|
|
588 | (2) |
|
Built-In Self Test (BIST) Techniques |
|
|
590 | (4) |
|
Current Monitoring IDDQ Test |
|
|
594 | (3) |
|
|
595 | (1) |
|
|
595 | (2) |
Appendix Design and Implementation of a 16-Bit Adder |
|
597 | (14) |
Index |
|
611 | |