Cmos Fractional-N Synthesizers,9781402073878

Cmos Fractional-N Synthesizers

by ;
ISBN13: 9781402073878
ISBN10: 1402073879
Format: Hardcover
Pub. Date: 2003-02-01
Publisher(s): Kluwer Academic Pub
List Price: $349.99

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Summary

CMOS Fractional-N Synthesizers fits in the quest for small and cheap cellular transceiver solutions. The book is conceived as a manual for the design of fully integrated DeltaSigma fractional-N frequency synthesizers in CMOS with a focus on achieving a high spectral purity, i.e. low-phase-noise and high spurious suppression. Fractional-N design is elaborated from specification derivation up to architectural and building block level and down to circuit level. CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers. CMOS Fractional-N Synthesizers covers the total design flow of monolithic CMOS fractional-N synthesizers with high spectral purity while providing insight in the most critical issues of monolithic fractional-N synthesis. All material is experimentally verified with several CMOS implementations, with ultimately a monolithic CMOS &Dgr;&Sgr;-controlled fractional-N synthesizer, which was part of a CMOS DCS-1800 transceiver front-end. The book is essential reading for analog and RF design engineers and researchers in the field and it is also suitable as text book for an advanced course on the subject.

Table of Contents

I Abstract v
List of Symbols and Abbreviations
vii
Table of Contents
xiii
Introduction
1(12)
Telecommunications: An Overview
1(2)
Telecommunications: A Market Perception
3(1)
Integration: Why, How and In What?
4(5)
P-Words
5(1)
Direct Conversion Transceivers
6(1)
CMOS Technology
7(1)
Trends in Research Evolution
8(1)
The Research Book
9(2)
The Outline of the Book
11(2)
On Frequency Synthesis
13(40)
Introduction
13(1)
Indirect or Phase-Locked Loop Frequency Synthesizers
14(3)
Phase-Lock
14(2)
Phase-Lock Frequency Synthesis Fundamentals
16(1)
The Synthesizer Data Sheet
17(8)
Spectral Purity
17(1)
Definition of Phase Noise
17(3)
Phase Noise in a PLL
20(2)
rms Phase Error
22(1)
Spurious Suppression
23(1)
Loop Dynamics
23(1)
Tracking and Settling
23(1)
Acquisition
24(1)
Other Specifications
25(1)
Introduction to PLL building blocks
25(13)
The Phase Detector
25(1)
Analog Phase Detectors
25(1)
The EXOR Phase Detector
26(1)
Flipflop Phase Detectors
26(1)
The Phase-Frequency Detector
27(2)
The Loop Filter
29(1)
Second-Order PLLs
29(4)
Third-Order PLLs
33(1)
The Oscillator
33(1)
The Xtal Oscillator
34(1)
The Relaxation Oscillator
35(1)
The Ring Oscillator
35(1)
The LC Oscillator
36(1)
Other Oscillator Types
36(1)
The Frequency Divider
36(1)
Programmable Dividers
37(1)
Advanced PLL Frequency Synthesizers
38(3)
Combining Frequency Synthesizers
39(1)
Fractional-N Frequency Synthesizers
40(1)
Frequency Synthesis for the DCS-1800 System
41(9)
A Fully Integrated DCS-1800 Transceiver
41(2)
The DCS-1800 Communication System
43(1)
From DCS-1800 to Synthesizer Specifications
44(1)
From Bit-error Rate to Signal-to-Noise Ratio
44(2)
Phase Noise
46(1)
Spurious Suppression
46(2)
rms Phase Error
48(1)
Dynamic Performance
49(1)
Specification Summary
50(1)
Conclusion
50(3)
High-Speed CMOS Prescalers
53(32)
Introduction
53(1)
The Phase-Switching Dual-Modulus Prescaler
54(4)
Conventional Architecture
54(2)
The Phase-Switching Architecture
56(2)
A Single-Ended 1.5 GHz 8/9 Dual-Modulus Prescaler in 0.7 μm CMOS
58(9)
The High-Speed Divide-by-2 D-flipflop
58(2)
The Half-speed Divide-by-2 D-flipflop
60(1)
Phase Noise Considerations
61(2)
Experimental Results
63(1)
General Results
63(2)
Phase Noise Results
65(2)
Design Issue: The Quadrature Accuracy
67(1)
A Single-ended 1.8 GHz 8/9 DMP in 0.8 μm ``Radiation Hardened'' BiCMOS
67(4)
The Circuit Implementation
67(3)
Experimental Results
70(1)
A 1.8 GHz 16-modulus /64-/79 Prescaler in 0.25 μm CMOS
71(4)
The Divide-by-2 Flipflops
71(2)
The Multi-Modulus Implementation
73(1)
Experimental Results
74(1)
A 12 GHz/128 Prescaler in 0.25 μm CMOS
75(7)
Introduction
75(1)
The Circuit Implementation
76(1)
The High-Speed Divide-by-2 Flipflop
76(1)
The Divide-by-128 Prescaler
77(1)
The Input Section
78(1)
Experimental Results
79(3)
Conclusion
82(3)
Monolithic CMOS LC-VCOs
85(52)
Introduction
85(1)
General Oscillator Theory
86(2)
A Design-Oriented Non-Linear Phase Noise Theory
88(7)
The Theory
88(1)
Modeling of the Non-Linear Active Element
88(2)
Phase Noise Analysis
90(3)
Comparison with Other Published Theories
93(2)
Integrated LC-tanks in CMOS
95(12)
Introduction
95(1)
Integrated Planar Inductors in Standard CMOS
96(1)
First Order Planar Inductor Model
96(1)
Losses in Integrated Planar Inductors
97(4)
The Simulator-Optimizer
101(2)
The Balanced Octagonal Inductor and Its Model
103(2)
Integrated Varactors in Standard CMOS
105(2)
The VCO Circuit Design
107(9)
General VCO Circuit Design
107(2)
Bipolar or CMOS?
109(1)
The Power Efficiency of VCO Circuits
110(1)
Hand Calculation MOS Model
110(2)
Complementary MOS or xMOS-only VCO?
112(1)
NMOS-only or PMOS-only VCO?
113(1)
1/f3 Phase Noise Mechanisms and Minimization
113(3)
Implementations
116(14)
A 2 GHz Low-Phase-Noise LC-VCO Set with Flicker Noise Minimization in 0.65 μm (Bi)CMOS
116(1)
Inductor Design
116(2)
VCO Design with Flicker Noise Minimization
118(2)
Experimental Results
120(3)
Extremely Low-Phase-Noise Measurement at 2.02 GHz: -132.5 dBc/Hz at 600 kHz and No Flicker Noise Upconversion!!
123(2)
A 1.8 GHz Highly-Tunable Low-Phase-Noise VCO in 0.25 μm CMOS
125(1)
Inductor Design
125(1)
VCO Design
125(3)
Experimental Results
128(1)
Quadrature Operation
129(1)
Comparison with Published State-of-the-Art VCOs
130(3)
Conclusion
133(4)
Monolithic Phase-Locked Loops
137(26)
Introduction
137(1)
Loop Filter Topology Selection
138(4)
Charge Pump PLL
139(2)
Fourth-Order PLL
141(1)
Dual-Path Fourth-Order PLL
142(11)
Dual-Path Filter Topology
143(1)
Transfer Functions
144(1)
Open Loop Gain
144(1)
Charge Pump Noise
145(1)
Loop Filter Noise
146(1)
Filter Optimization
147(5)
Conventional Versus Dual-Path Topologies
152(1)
The PLL Building Block Circuits
153(3)
The 3-step Equalizer Circuit
153(2)
The Loop Filter Circuit
155(1)
Experimental Results
156(5)
Conclusion
161(2)
A 1.8 GHz CMOS Δ Σ Fractional-N Frequency Synthesizer
163(58)
Introduction
163(1)
The Fractional-N Principle
164(3)
Conventional Fractional Compensation Methods
167(2)
The Analog Phase Interpolator
167(1)
The Fractional Divider
168(1)
Δ Σ Modulation in Fractional-N Synthesis
169(4)
Introduction
169(1)
The Accumulator as Noise-Shaping Quantizer
169(1)
General Δ Σ Modulator Theory
170(2)
Δ Σ Modulators with DC-inputs
172(1)
Δ Σ Modulators for Fractional-N Synthesis
173(5)
The MASH Modulator
174(1)
The Multi-Bit, Single-Loop Δ Σ Modulator
175(3)
The Theoretical Δ Σ Phase Noise Analysis
178(7)
The Out-of-Band Δ Σ Phase Noise
179(4)
The Δ Σ rms Phase Error
183(2)
A Fast Non-Linear Δ Σ Phase Noise Analysis Method
185(12)
The Analysis Method
186(3)
Analysis Results
189(6)
Analysis Results: The Origin of Spurious Tones
195(2)
The Fractional-N Synthesizer Circuit Design
197(8)
The Phase-Frequency Detector
198(2)
The Charge Pumps
200(1)
The Spurious Suppression
201(3)
The Gain Mismatch
204(1)
Experimental Results
205(13)
Measurement Setup
205(2)
Measurement Results
207(8)
Comparison with Published Δ Σ Fractional-N Synthesizers
215(3)
Conclusion
218(3)
Conclusions
221(8)
A 2V CMOS Cellular Transceiver Front-End
221(4)
Main Contributions and Achievements
225(2)
Epilogue
227(2)
Δ Σ Modulators with DC-inputs 229(4)
Additional Results of the Non-Linear Analysis for Δ Σ Fractional-N Synthesizers 233(6)
Index 239(4)
Bibliography 243

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