Compilation Techniques for Reconfigurable Architectures

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Format: Hardcover
Pub. Date: 2008-10-17
Publisher(s): Springer Verlag
List Price: $169.00

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Summary

"This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges - particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs)." "Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures."--BOOK JACKET.

Table of Contents

Introductionp. 1
The Promise of Reconfigurable Architectures and Systemsp. 1
The Challenge: How to Program and Compile for Reconfigurable Systems?p. 3
This Book: Key Techniques when Compiling to Reconfigurable Architecturep. 4
Organization of this Bookp. 5
Overview of Reconfigurable Architecturesp. 7
Evolution of Reconfigurable Architecturesp. 7
Reconfigurable Architectures: Key Characteristicsp. 8
Granularityp. 10
Fine-Grained Reconfigurable Architecturesp. 12
Coarse-Grained Reconfigurable Architecturesp. 14
Hybrid Reconfigurable Architecturesp. 16
Granularity and Mappingp. 19
Interconnection Topologiesp. 20
System-Level Integrationp. 21
Dynamic Reconfigurationp. 24
Computational and Execution Modelsp. 29
Streaming Data Input and Outputp. 31
Summaryp. 31
Compilation and Synthesis Flowsp. 33
Overviewp. 33
Front-Endp. 34
Middle-Endp. 35
Back-Endp. 37
Hardware Compilation and High-Level Synthesisp. 39
Generic High-Level Synthesisp. 40
Customized High-Level Synthesis for Fine-Grained Reconfigurable Architecturesp. 41
Register-Transfer-Level/Logic Synthesisp. 45
High-Level Compilation for Coarse-Grained Reconfigurable Architecturesp. 48
Placement and Routingp. 49
Illustrative Examplep. 51
High-Level Source Code Examplep. 51
Data-Flow Representationp. 52
Computation-Oriented Mapping and Schedulingp. 53
Data-Oriented Mapping and Transformationsp. 55
Translation to Hardwarep. 58
Reconfigurable Computing Issues and Their Impact on Compilationp. 59
Programming Languages and Execution Modelsp. 61
Intermediate Representationsp. 62
Target Reconfigurable Architecture Featuresp. 64
Summaryp. 65
Code Transformationsp. 67
Bit-Level Transformationsp. 67
Bit-Width Narrowingp. 68
Bit-Level Optimizationsp. 72
Conversion from Floating- to Fixed-Point Representationsp. 75
Nonstandard Floating-Point Formatsp. 77
Instruction-Level Transformationsp. 77
Operator Strength Reductionp. 78
Height Reductionp. 80
Code Motionp. 84
Loop-Level Transformationsp. 87
Loop Unrollingp. 87
Loop Tiling and Loop Strip-Miningp. 90
Loop Merging and Loop Distributionp. 94
Data-Oriented Transformationsp. 95
Data Distributionp. 95
Data Replicationp. 96
Data Reuse and Scalar Replacement in Registers and Internal RAMsp. 96
Other Data-Oriented Transformationsp. 99
Function-Oriented Transformationsp. 101
Function Inlining and Outliningp. 101
Recursive Functionsp. 104
Which Code Transformations to Choose?p. 105
Summaryp. 107
Mapping and Execution Optimizationsp. 109
Hardware Execution Techniquesp. 109
Instruction-Level Parallelismp. 110
Speculative Executionp. 112
Predication and if-conversionp. 114
Multi Taskingp. 116
Partitioningp. 118
Temporal Partitioningp. 119
Spatial Partitioningp. 124
Illustrative Examplep. 125
Mapping Program Constructs to Resourcesp. 127
Mapping Scalar Variables to Registersp. 127
Mapping of Operations to FUsp. 129
Mapping of Selection Structuresp. 130
Sharing Functional Units FUsp. 131
Combining Instructions for RFUsp. 132
Pipeliningp. 134
Pipelined Functional and Execution Unitsp. 135
Pipelining Memory Accessesp. 138
Loop Pipeliningp. 139
Coarse-Grained Pipeliningp. 144
Pipelining Configuration-Computation Sequencesp. 145
Memory Accessesp. 146
Partitioning and Mapping of Arrays to Memory Resourcesp. 146
Improving Memory Accessesp. 148
Back-End Supportp. 150
Allocation, Scheduling, and Bindingp. 150
Module Generationp. 151
Mapping, Placement, and Routingp. 153
Summaryp. 153
Compilers for Reconfigurable Architecturesp. 155
Early Compilation Effortsp. 155
Compilers for FPGA-Based Systemsp. 157
The SPC Compilerp. 157
A C to Fine-Grained Pipelining Compilerp. 158
The DeepC Silicon Compilerp. 158
The COBRA-ABS Toolp. 158
The DEFACTO Compilerp. 159
The Streams-C Compilerp. 159
The Cameron Compilerp. 160
The MATCH Compilerp. 160
The Galadriel and Nenya Compilersp. 161
The Sea Cucumber Compilerp. 161
The Abstract-Machines Compilerp. 161
The CHAMPION Software Design Environmentp. 162
The SPARCS Toolp. 163
The ROCCC Compilerp. 163
The DWARV Compilerp. 163
Compilers for Coarse-Grained Reconfigurable Architecturesp. 164
The DIL Compilerp. 164
The RaPiD-C Compilerp. 165
The CoDe-X Compilerp. 165
The XPP-VC Compilerp. 166
The DRESC Compilerp. 166
Compilers for Hybrid Reconfigurable Architecturesp. 167
The Chimaera-C Compilerp. 167
The Garp and the Nimble C Compilersp. 168
The NAPA-C Compilerp. 168
Compilation Efforts Summaryp. 169
Perspectives on Programming Reconfigurable Computing Platformsp. 177
How to Make Reconfigurable Computing a Reality?p. 177
Easy of Programmingp. 178
Program Portability and Legacy Code Migrationp. 179
Performance Portabilityp. 180
Research Directions in Compilation for Reconfigurable Architecturesp. 181
Programming Language Designp. 181
Intermediate Representationp. 181
Mapping to Multiple Computing Enginesp. 182
Code Transformationsp. 182
Design-Space Exploration and Compilation Timep. 183
Pipelined Executionp. 184
Memory Mapping Optimizationsp. 185
Application-Specific Compilers and Coresp. 185
Resource Virtualizationp. 186
Dynamic and Incremental Compilationp. 186
Tackling the Compilation Challenge for Reconfigurable Architecturesp. 187
Reconfigurable Architectures and Nanotechnologyp. 189
Summaryp. 189
Final Remarksp. 191
Referencesp. 193
List of Acronymsp. 213
Indexp. 217
Table of Contents provided by Ingram. All Rights Reserved.

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