Semiconductor Memories Technology, Testing, and Reliability,9780780310001

Semiconductor Memories Technology, Testing, and Reliability

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Edition: 1st
ISBN13: 9780780310001
ISBN10: 0780310004
Format: Hardcover
Pub. Date: 2002-09-10
Publisher(s): Wiley-IEEE Press
List Price: $255.94

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Summary

Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including. * Memory cell structures and fabrication technologies. * Application-specific memories and architectures. * Memory design, fault modeling and test algorithms, limitations, and trade-offs. * Space environment, radiation hardening process and design techniques, and radiation testing. * Memory stacks and multichip modules for gigabyte storage.

Author Biography

ASHOK K. SHARMA is the author of Semiconductor Memories: Technology, Testing, and Reliability. He is currently working as a reliability engineering manager at NASA, Goddard Space Flight Center, Greenbelt, Maryland.

Table of Contents

Preface xi
Introduction
1(9)
Random Access Memory Technologies
10(71)
Introduction
10(2)
Static Random Access Memories (SRAMs)
12(28)
SRAM (NMOS and CMOS) Cell Structures
12(2)
MOS SRAM Architectures
14(1)
MOS SRAM Cell and Peripheral Circuit Operation
15(2)
Bipolar SRAM Technologies
17(1)
Direct-Coupled Transistor Logic (DCTL) Technology
18(1)
Emitter-Coupled Logic (ECL) Technology
19(1)
BiCMOS Technology
20(4)
Silicon-on-Insulator (SOI) Technology
24(4)
Advanced SRAM Architectures and Technologies
28(1)
1--4 Mb SRAM Designs
28(4)
16--64 Mb SRAM Development
32(2)
Gallium Arsenide (GaAs) SRAMs
34(1)
Application-Specific SRAMs
35(1)
Serially Accessed Memory (Line Buffers)
35(1)
Dual-Port RAMs
36(2)
Nonvolatile SRAMs
38(1)
Content-Addressable Memories (CAMs)
38(2)
Dynamic Random Access Memories (DRAMs)
40(41)
DRAM Technology Development
40(5)
CMOS DRAMs
45(2)
1 Mb DRAM (Example)
47(3)
DRAM Cell Theory and Advanced Cell Structures
50(2)
Trench Capacitor Cells
52(3)
Stacked Capacitor Cells (STC)
55(3)
BiCMOS DRAMs
58(2)
Soft-Error Failures in DRAMs
60(2)
Advanced DRAM Designs and Architectures
62(1)
A 16 Mb DRAM (Example)
63(1)
ULSI DRAM Developments
64(5)
Application-Specific DRAMs
69(1)
Pseudostatic DRAMs (PSRAMs)
69(1)
Silicon File
69(1)
Video DRAMs (VRAMs)
70(1)
High-Speed DRAMs
71(4)
Application-Specific RAM Glossary and Summary of Important Characteristics
75(6)
Nonvolatile Memories
81(59)
Introduction
81(2)
Masked Read-Only Memories (ROMs)
83(4)
Technology Development and Cell Programming
83(2)
ROM Cell Structures
85(2)
High-Density (Multimegabit) ROMs
87(1)
Programmable Read-Only Memories (PROMs)
87(6)
Bipolar PROMs
87(4)
CMOS PROMs
91(2)
Erasable (UV)-Programmable Read-Only Memories (EPROMs)
93(11)
Floating-Gate EPROM Cell
93(3)
EPROM Technology Developments
96(1)
1 Mb EPROM (Example)
97(1)
Advanced EPROM Architectures
98(5)
One-Time Programmable (OTP) EPROMs
103(1)
Electrically Erasable PROMs (EEPROMs)
104(18)
EEPROM Technologies
105(1)
Metal--Nitride--Oxide Silicon (MNOS) Memories
105(4)
Silicon--Oxide Nitride--Oxide Semiconductor (SONOS) Memories
109(1)
Floating-Gate Tunneling Oxide (FLOTOX) Technology
110(5)
Textured-Polysilicon Technology
115(1)
EEPROM Architectures
116(4)
Nonvolatile SRAM (or Shadow RAM)
120(2)
Flash Memories (EPROMs or EEPROMs)
122(18)
Flash Memory Cells and Technology Developments
123(5)
Advanced Flash Memory Architectures
128(12)
Memory Fault Modeling and Testing
140(55)
Introduction
140(2)
RAM Fault Modeling
142(16)
Stuck-At Fault Model
142(3)
Bridging Faults
145(2)
Coupling Faults
147(4)
Pattern-Sensitive Faults
151(4)
Miscellaneous Faults
155(1)
GaAs SRAM Fault Modeling and Testing
155(1)
Embedded DRAM Fault Modeling and Testing
156(2)
RAM Electrical Testing
158(18)
DC and AC Parametric Testing
158(1)
Functional Testing and some Commonly Used Algorithms
158(16)
Functional Test Pattern Selection
174(2)
RAM Pseudorandom Testing
176(2)
Megabit DRAM Testing
178(2)
Nonvolatile Memory Modeling and Testing
180(5)
DC Electrical Measurements
181(1)
AC (Dynamic) and Functional Measurements
182(1)
256K UVEPROM
182(1)
64K EEPROM
183(2)
IDDQ Fault Modeling and Testing
185(4)
Application Specific Memory Testing
189(6)
General Testing Requirements
189(2)
Double-Buffered Memory (DBM) Testing
191(4)
Memory Design for Testability and Fault Tolerance
195(54)
General Design for Testability Techniques
195(8)
Ad Hoc Design Techniques
196(1)
Logic Partitioning
196(1)
Input/Output Test Points
196(1)
Structured Design Techniques
197(1)
Level-Sensitive Scan Design
197(2)
Scan Path
199(1)
Scan/Set Logic
199(1)
Random Access Scan
200(2)
Boundary Scan Testing
202(1)
RAM Built-In Self-Test (BIST)
203(8)
BIST Using Algorithmic Test Sequence
205(2)
BIST Using 13N March Algorithm
207(2)
BIST for Pattern-Sensitive Faults
209(1)
BIST Using Built-In Logic Block Observation (BILBO)
210(1)
Embedded Memory DFT and BIST Techniques
211(5)
Advanced BIST and Built-In Self-Repair Architectures
216(12)
Multibit and Line Mode Tests
216(3)
Column Address-Maskable Parallel Test (CMT) Architecture
219(1)
BIST Scheme Using Microprogram ROM
220(2)
BIST and Built-In Self-Repair (BISR) Techniques
222(6)
DFT and BIST for ROMs
228(2)
Memory Error-Detection and Correction Techniques
230(11)
Memory Fault-Tolerance Designs
241(8)
Semiconductor Memory Reliability
249(71)
General Reliability Issues
249(9)
Semiconductor Bulk Failures
252(1)
Dielectric-Related Failures
252(1)
Semiconductor--Dielectric Interface Failures
253(2)
Conductor and Metallization Failures
255(1)
Metallization Corrosion-Related Failures
256(1)
Assembly-and Packaging-Related Failures
257(1)
RAM Failure Modes and Mechanisms
258(10)
RAM Gate Oxide Reliability
258(2)
RAM Hot-Carrier Degradation
260(2)
DRAM Capacitor Reliability
262(1)
Trench Capacitors
262(2)
Stacked Capacitors
264(1)
DRAM Soft-Error Failures
264(3)
DRAM Data-Retention Properties
267(1)
Nonvolatile Memory Reliability
268(19)
Programmable Read-Only Memory (PROM) Fusible Links
268(2)
EPROM Data Retention and Charge Loss
270(5)
Electrically Erasable Programmable Read-Only Memories (EEPROMs)
275(5)
Flash Memories
280(3)
Ferroelectric Memories
283(4)
Reliability Modeling and Failure Rate Prediction
287(9)
Reliability Definitions and Statistical Distributions
287(2)
Binomial Distribution
289(1)
Poisson Distribution
289(1)
Normal (or Gaussian) Distribution
289(2)
Exponential Distribution
291(1)
Gamma Distribution
291(1)
Weibull Distribution
291(1)
Lognormal Distribution
292(1)
Reliability Modeling and Failure Rate Prediction
292(4)
Design for Reliability
296(4)
Reliability Test Structures
300(4)
Reliability Screening and Qualification
304(16)
Reliability Testing
304(6)
Screening, Qualification, and Quality Conformance Inspections (QCI)
310(10)
Semiconductor Memory Radiation Effects
320(67)
Introduction
320(2)
Radiation Effects
322(25)
Space Radiation Environments
322(3)
Total Dose Effects
325(5)
Single-Event Phenomenon (SEP)
330(3)
DRAM and SRAM Upsets
333(2)
SEU Modeling and Error Rate Prediction
335(2)
SEP In-Orbit Flight Data
337(7)
Nonvolatile Memory Radiation Characteristics
344(3)
Radiation-Hardening Techniques
347(20)
Radiation-Hardening Process Issues
347(1)
Substrate Effects
347(1)
Gate Oxide (Dielectric) Effects
347(1)
Gate Electrode Effects
348(1)
Postgate-Electrode Deposition Processing
349(1)
Field Oxide Hardening
349(1)
Bulk CMOS Latchup Considerations
350(1)
CMOS SOS/SOI Processes
351(1)
Bipolar Process Radiation Characteristics
352(1)
Radiation-Hardening Design Issues
352(1)
Total Dose Radiation Hardness
353(5)
Single-Event Upset (SEU) Hardening
358(5)
Radiation-Hardened Memory Characteristics (Example)
363(4)
Radiation Hardness Assurance and Testing
367(20)
Radiation Hardness Assurance
367(2)
Radiation Testing
369(1)
Total Dose Testing
370(2)
Single-Event Phenomenon (SEP) Testing
372(4)
Dose Rate Transient Effects
376(1)
Neutron Irradiation
377(1)
Radiation Dosimetry
377(1)
Wafer Level Radiation Testing and Test Structures
378(1)
Wafer Level Radiation Testing
378(1)
Radiation Test Structures
379(8)
Advanced Memory Technologies
387(25)
Introduction
387(2)
Ferroelectric Random Access Memories (FRAMs)
389(8)
Basic Theory
389(1)
FRAM Cell and Memory Operation
390(3)
FRAM Technology Developments
393(1)
FRAM Reliability Issues
393(2)
FRAM Radiation Effects
395(2)
FRAMs Versus EEPROMs
397(1)
Gallium Arsenide (GaAs) FRAMs
397(1)
Analog Memories
398(3)
Magnetoresistive Random Access Memories (MRAMs)
401(6)
Experimental Memory Devices
407(5)
Quantum--Mechanical Switch Memories
407(1)
A GaAs n-p-n-p Thyristor/JFET Memory Cell
408(1)
Single-Electron Memory
409(1)
Neuron-MOS Multiple-Valued (MV) Memory Technology
409(3)
High-Density Memory Packaging Technologies
412(39)
Introduction
412(5)
Memory Hybrids and MCMs (2-D)
417(7)
Memory Modules (Commercial)
417(4)
Memory MCMs (Honeywell ASCM)
421(1)
VLSI Chip-on-Silicon (VCOS) Technology
421(3)
Memory Stacks and MCMs (3-D)
424(11)
3-D Memory Stacks (Irvine Sensors Corporation)
427(2)
4 Mb SRAM Short Stack (TM) (Example)
429(1)
3-D Memory Cube Technology (Thomson CSF)
430(1)
3-D Memory MCMs (GE-HDI/TI)
431(1)
3-D HDI Solid-State Recorder (Example)
432(1)
3-D Memory Stacks (n CHIPS)
432(3)
Memory MCM Testing and Reliability Issues
435(5)
VCOS DFT Methodology and Screening Flow (Example)
437(3)
Memory Cards
440(6)
CMO SRAM Card (Example)
442(1)
Flash Memory Cards
442(4)
High-Density Memory Packaging Future Directions
446(5)
Index 451

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